1. Technical Field
The present invention relates to an analog-to-digital conversion technology, and more particularly to a successive-approximation-register (SAR) analog-to-digital converter (ADC) and a method thereof.
2. Related Art
An ADC is of various architectures, such as: a flash ADC, a pipelined ADC, and an SAR ADC. These architectures have respective advantages, and are generally selected according to different application demands. Compared with other architectures, the SAR ADC is lower in power consumption, smaller in area and lower in cost.
Conventionally, an SAR ADC obtains a digital output code matching an input signal by adopting a binary search algorithm. In a converting procedure, according to a comparison result of a comparer each time, in a digital-to-analog converting circuit in the SAR ADC, a binary scaled voltage generally needs to be added or subtracted, and after a last bit cycle ends, the difference between an input signal and a reference voltage is less than a least significant bit (LSB). However, when the input signal is small, the input signal is easily subjected to interference of a noise (this interference includes interference of the comparer, interference of a chip system itself, and interference of a power source), and thus there is occurrence of misjudgment in the converting procedure.